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<span id="openzim-page-title" class="mw-page-title-main">eSi-RISC</span>
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</style><table class="infobox"><caption class="infobox-title">eSi-RISC</caption><tbody><tr><th scope="row" class="infobox-label">Designer</th><td class="infobox-data">eSi-RISC</td></tr><tr><th scope="row" class="infobox-label">Bits</th><td class="infobox-data">16-bit/32-bit</td></tr><tr><th scope="row" class="infobox-label">Introduced</th><td class="infobox-data">2009</td></tr><tr><th scope="row" class="infobox-label"><a href="Computer_architecture" title="Computer architecture">Design</a></th><td class="infobox-data">RISC</td></tr><tr><th scope="row" class="infobox-label">Type</th><td class="infobox-data"><a href="Load%E2%80%93store" class="mw-redirect" title="Load–store">Load–store</a></td></tr><tr><th scope="row" class="infobox-label"><a href="Instruction_set" class="mw-redirect" title="Instruction set">Encoding</a></th><td class="infobox-data">Intermixed 16 and 32-bit</td></tr><tr><th scope="row" class="infobox-label"><a href="Branch_(computer_science)" title="Branch (computer science)">Branching</a></th><td class="infobox-data">Compare and branch and condition code</td></tr><tr><th scope="row" class="infobox-label"><a href="Endianness" title="Endianness">Endianness</a></th><td class="infobox-data">Big or little</td></tr><tr><th scope="row" class="infobox-label">Extensions</th><td class="infobox-data">User-defined instructions</td></tr><tr><th colspan="2" class="infobox-header"><a href="Processor_register" title="Processor register">Registers</a></th></tr><tr><td colspan="2" class="infobox-full-data">8/16/32 General Purpose, 8/16/32 Vector</td></tr></tbody></table>
<p><b>eSi-RISC</b> is a configurable <a href="CPU" class="mw-redirect" title="CPU">CPU</a> architecture. It is available in five implementations: the eSi-1600, eSi-1650, eSi-3200, eSi-3250 and eSi-3264.<sup id="cite_ref-1" class="reference"><a href="#cite_note-1"><span class="cite-bracket">[</span>1<span class="cite-bracket">]</span></a></sup> The eSi-1600 and eSi-1650 feature a <a href="16-bit" class="mw-redirect" title="16-bit">16-bit</a> data-path, while the eSi-32x0s feature <a href="32-bit" class="mw-redirect" title="32-bit">32-bit</a> data-paths, and the eSi-3264 features a mixed 32/64-bit datapath. Each of these processors is licensed as soft <a href="IP_core" class="mw-redirect" title="IP core">IP cores</a>, suitable for integrating into both <a href="Application-specific_integrated_circuit" title="Application-specific integrated circuit">ASICs</a> and <a href="FPGA" class="mw-redirect" title="FPGA">FPGAs</a>.<sup id="cite_ref-2" class="reference"><a href="#cite_note-2"><span class="cite-bracket">[</span>2<span class="cite-bracket">]</span></a></sup>
</p>
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<div class="mw-heading mw-heading2"><h2 id="Architecture">Architecture</h2></div>
<p>The main features of the eSi-RISC architecture are:<sup id="cite_ref-3" class="reference"><a href="#cite_note-3"><span class="cite-bracket">[</span>3<span class="cite-bracket">]</span></a></sup>
</p>
<ul><li><a href="RISC" class="mw-redirect" title="RISC">RISC</a>-like load/store architecture.</li>
<li>Configurable 16-bit, 32-bit or 32/64-bit data-path.</li>
<li>Instructions are encoded in either 16 or 32-bits.</li>
<li>8, 16 or 32 general purpose registers, that are either 16 or 32-bits wide.</li>
<li>0, 8, 16 or 32 vector registers, that are either 32 or 64-bits wide.</li>
<li>Up to 32 external, vectored, nested and prioritizable interrupts.</li>
<li>Configurable instruction set including support for integer, floating-point and fixed-point arithmetic.</li>
<li><a href="SIMD" class="mw-redirect" title="SIMD">SIMD</a> operations.</li>
<li>Optional support for user-defined instructions, such as cryptographic acceleration .<sup id="cite_ref-4" class="reference"><a href="#cite_note-4"><span class="cite-bracket">[</span>4<span class="cite-bracket">]</span></a></sup></li>
<li>Optional caches (Configurable size and associativity).</li>
<li>Optional <a href="Memory_management_unit" title="Memory management unit">MMU</a> supporting both memory protection and dynamic address translation.</li>
<li><a href="Advanced_Microcontroller_Bus_Architecture" title="Advanced Microcontroller Bus Architecture">AMBA</a> AXI, AHB and APB bus interfaces.</li>
<li>Memory mapped I/O.</li>
<li>5-stage pipeline.</li>
<li>Hardware <a href="JTAG" title="JTAG">JTAG</a> debug.</li></ul>
<p>While there are many different 16 or 32-bit <a href="Soft_microprocessor" title="Soft microprocessor">Soft microprocessor</a> IP cores available, eSi-RISC is the only architecture licensed as an IP core that has both 16 and 32-bit implementations.
</p><p>Unlike in other RISC architectures supporting both 16 and 32-bit instructions, such as ARM/Thumb or MIPS/MIPS-16, 16 and 32-bit instructions in the eSi-RISC architecture can be freely intermixed, rather than having different modes where either all 16-bit instructions or all 32-bit instructions are executed. This improves code density without compromising performance. The 16-bit instructions support two register operands in the lower 16 registers, whereas the 32-bit instructions support three register operands and access to all 32 registers.
</p><p>eSi-RISC includes support for <a href="Multiprocessing" title="Multiprocessing">Multiprocessing</a>. Implementations have included up to seven eSi-3250's on a single chip.<sup id="cite_ref-5" class="reference"><a href="#cite_note-5"><span class="cite-bracket">[</span>5<span class="cite-bracket">]</span></a></sup>
</p>
<div class="mw-heading mw-heading2"><h2 id="Toolchain">Toolchain</h2></div>
<p>The eSi-RISC toolchain is based on combination of a port of the <a href="GNU_toolchain" title="GNU toolchain">GNU toolchain</a> and the <a href="Eclipse_ide" class="mw-redirect" title="Eclipse ide">Eclipse</a> <a href="Integrated_development_environment" title="Integrated development environment">IDE</a>.<sup id="cite_ref-6" class="reference"><a href="#cite_note-6"><span class="cite-bracket">[</span>6<span class="cite-bracket">]</span></a></sup> This includes:
</p>
<ul><li><a href="GNU_Compiler_Collection" title="GNU Compiler Collection">GCC</a> – C/C++ compiler.</li>
<li><a href="Binutils" class="mw-redirect" title="Binutils">Binutils</a> – Assembler, linker and binary utilities.</li>
<li><a href="GDB" class="mw-redirect" title="GDB">GDB</a> – Debugger.</li>
<li><a href="Eclipse_ide" class="mw-redirect" title="Eclipse ide">Eclipse</a> – Integrated Development Environment.</li></ul>
<p>The C library is <a href="Newlib" title="Newlib">Newlib</a> and the C++ library is <a href="Libstdc%2B%2B" class="mw-redirect" title="Libstdc++">Libstdc++</a>. Ported <a href="RTOS" class="mw-redirect" title="RTOS">RTOSes</a> include <a href="MicroC/OS-II" class="mw-redirect" title="MicroC/OS-II">MicroC/OS-II</a>, <a href="FreeRTOS" title="FreeRTOS">FreeRTOS</a>, <a href="ERIKA_Enterprise" title="ERIKA Enterprise">ERIKA Enterprise</a><sup id="cite_ref-7" class="reference"><a href="#cite_note-7"><span class="cite-bracket">[</span>7<span class="cite-bracket">]</span></a></sup> and <a href="Phoenix-RTOS" title="Phoenix-RTOS">Phoenix-RTOS</a><sup id="cite_ref-8" class="reference"><a href="#cite_note-8"><span class="cite-bracket">[</span>8<span class="cite-bracket">]</span></a></sup>
</p>
<div class="mw-heading mw-heading2"><h2 id="References">References</h2></div>
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<ol class="references">
<li id="cite_note-1"><span class="mw-cite-backlink"><b><a href="#cite_ref-1">^</a></b></span> <span class="reference-text"><a rel="nofollow" class="external autonumber" href="http://www.electronicsweekly.com/Articles/2009/11/17/47447/ensilicas-esi-risc-soft-processor-cores-are-aimed-at-socs.htm">[1]</a> Electronics Weekly, 17 November 2009</span>
</li>
<li id="cite_note-2"><span class="mw-cite-backlink"><b><a href="#cite_ref-2">^</a></b></span> <span class="reference-text"><a rel="nofollow" class="external autonumber" href="http://www.eetimes.eu/design/221800121">[2]</a> EE Times, 17 November 2009</span>
</li>
<li id="cite_note-3"><span class="mw-cite-backlink"><b><a href="#cite_ref-3">^</a></b></span> <span class="reference-text"><a rel="nofollow" class="external autonumber" href="https://www.esi-risc.com/risc-ip/esi-3250/">[3]</a> eSi-RISC eSi-3250 Technical Overview</span>
</li>
<li id="cite_note-4"><span class="mw-cite-backlink"><b><a href="#cite_ref-4">^</a></b></span> <span class="reference-text"><a rel="nofollow" class="external autonumber" href="http://www.electronicsweekly.com/news/components/microprocessors-and-dsps/ensilica-designs-secure-processor-with-kili-technology-2013-10/">[4]</a> Electronics Weekly, 2013</span>
</li>
<li id="cite_note-5"><span class="mw-cite-backlink"><b><a href="#cite_ref-5">^</a></b></span> <span class="reference-text"><a rel="nofollow" class="external autonumber" href="http://www.design-reuse.com/news/26334/ensilica-posedge-deal.html">[5]</a> Design & Reuse, 2011</span>
</li>
<li id="cite_note-6"><span class="mw-cite-backlink"><b><a href="#cite_ref-6">^</a></b></span> <span class="reference-text"><a rel="nofollow" class="external autonumber" href="http://www.ensilica.com/pdfs/EnSilica%20A4_Flyer_eSi-RISC%20IP.PDF">[6]</a> <a rel="nofollow" class="external text" href="https://web.archive.org/web/20120228234558/http://www.ensilica.com/pdfs/EnSilica%20A4_Flyer_eSi-RISC%20IP.PDF">Archived</a> 28 February 2012 at the <a href="Wayback_Machine" title="Wayback Machine">Wayback Machine</a> EnSilica, 2009</span>
</li>
<li id="cite_note-7"><span class="mw-cite-backlink"><b><a href="#cite_ref-7">^</a></b></span> <span class="reference-text"><a rel="nofollow" class="external autonumber" href="http://www.electronicsweekly.com/Articles/2010/10/07/49603/open-source-rtos-targets-automotive-systems.htm">[7]</a> Electronics Weekly, 2010,</span>
</li>
<li id="cite_note-8"><span class="mw-cite-backlink"><b><a href="#cite_ref-8">^</a></b></span> <span class="reference-text"><a rel="nofollow" class="external autonumber" href="https://web.archive.org/web/20131211141823/http://www.cambridgenetwork.co.uk/news/phoenix-ports-phoenix-rtos-to-ensilica-s-esi-risc/">[8]</a> Cambridge Network 2013</span>
</li>
</ol></div>
<div class="mw-heading mw-heading2"><h2 id="External_links">External links</h2></div>
<ul><li><a rel="nofollow" class="external text" href="http://www.esi-risc.com/">eSi-RISC homepage</a></li></ul>
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</style><div id="Reduced_instruction_set_computer_(RISC)_architectures114" style="font-size:114%;margin:0 4em"><a href="Reduced_instruction_set_computer" title="Reduced instruction set computer">Reduced instruction set computer</a> (RISC) architectures</div></th></tr><tr><th scope="row" class="navbox-group" style="width:1%">Origins</th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em">
<ul><li><a href="IBM_801" title="IBM 801">IBM 801</a></li>
<li><a href="Berkeley_RISC" title="Berkeley RISC">Berkeley RISC</a></li>
<li><a href="Stanford_MIPS" title="Stanford MIPS">Stanford MIPS</a></li></ul>
</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Development<br>active</th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em">
<ul><li><a href="Blackfin" title="Blackfin">Analog Devices Blackfin</a></li>
<li><a href="ARC_(processor)" title="ARC (processor)">ARC</a></li>
<li><a href="ARM_architecture_family" title="ARM architecture family">ARM</a></li>
<li><a href="AVR_microcontrollers" title="AVR microcontrollers">AVR</a></li>
<li><a href="LatticeMico8" title="LatticeMico8">LatticeMico8</a>, <a href="LatticeMico32" title="LatticeMico32">LatticeMico32</a></li>
<li><a href="MIPS_architecture" title="MIPS architecture">MIPS</a></li>
<li><a href="OpenRISC" title="OpenRISC">OpenRISC</a></li>
<li><a href="Power_ISA" title="Power ISA">Power ISA</a></li>
<li><a href="Renesas_Electronics" title="Renesas Electronics">Renesas</a> <a href="M32R" title="M32R">M32R</a>, <a href="SuperH" title="SuperH">SuperH</a>, <a href="V850" title="V850">V850</a></li>
<li><a href="RISC-V" title="RISC-V">RISC-V</a></li>
<li><a href="SPARC" title="SPARC">SPARC</a></li>
<li><a href="Sunway_(processor)" title="Sunway (processor)">Sunway</a></li>
<li><a href="Unicore" title="Unicore">Unicore</a></li>
<li><a href="Xilinx" title="Xilinx">Xilinx</a> <a href="MicroBlaze" title="MicroBlaze">MicroBlaze</a>, <a href="PicoBlaze" title="PicoBlaze">PicoBlaze</a></li></ul>
</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Development<br>discontinued</th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em">
<ul><li><a href="DEC_Alpha" title="DEC Alpha">Alpha</a></li>
<li><a href="AMD_Am29000" title="AMD Am29000">AMD Am29000</a></li>
<li><a href="Apollo_PRISM" title="Apollo PRISM">Apollo PRISM</a></li>
<li><a href="Atmel" title="Atmel">Atmel</a> <a href="AVR32" title="AVR32">AVR32</a></li>
<li><a href="Clipper_architecture" title="Clipper architecture">Clipper</a></li>
<li><a href="CompactRISC" title="CompactRISC">CR16</a></li>
<li><a href="AT%26T_Hobbit" title="AT&T Hobbit">CRISP</a></li>
<li><a href="DEC_PRISM" title="DEC PRISM">DEC PRISM</a></li>
<li><a href="Intel_i860" title="Intel i860">Intel i860</a>, <a href="Intel_i960" title="Intel i960">i960</a></li>
<li><a href="Imagination_META" title="Imagination META">META</a></li>
<li><a href="MIPS-X" title="MIPS-X">MIPS-X</a></li>
<li><a href="Motorola_88000" title="Motorola 88000">Motorola 88000</a>, <a href="M%C2%B7CORE" title="M·CORE">M·CORE</a></li>
<li><a href="PA-RISC" title="PA-RISC">PA-RISC</a></li>
<li><a href="IBM_POWER_architecture" title="IBM POWER architecture">POWER</a>, <a href="PowerPC" title="PowerPC">PowerPC</a> <i>(active use in space exploration as <a href="RAD750" title="RAD750">RAD750</a>)</i>, <a href="IBM_ROMP" title="IBM ROMP">ROMP</a></li></ul>
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This article is issued from <a class="external text" title="Last edited on 2025-01-17" href="https://en.wikipedia.org/wiki/?title=ESi-RISC&oldid=1269956582">Wikipedia</a>. The text is available under <a class="external text" href="https://creativecommons.org/licenses/by-sa/4.0/deed.en">Creative Commons Attribution-Share Alike 4.0</a> unless otherwise noted. Additional terms may apply for the media files.
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